Problems

A processor with a single core runs a process consisting of two threads. Thread 1 has a higher priority than thread 2. Thread 1 claims a semaphore \(S_1\) for a mutually exclusive resource \(0.2\) s after the start of process execution. It later releases the semaphore \(0.5\) s after the start of process execution. Thread 2 starts \(0.3\) s after the process starts executing and immediately requires the resource with semaphore \(S_1\). After the process has been executing for \(0.4\) s, which thread is currently running? What if the thread priority is reversed?

Consider the logic diagram here.

Use symbolic propositional logic or Boolean algebra to reduce the number of logic gates in the system as much as possible, while maintaining the same functionality.

NAND gates are inexpensive because they can be easily manufactured and are functionally complete. This means that all logic gates can be constructed out of NAND gates. How can the following logic gates be constructed out of NAND gates?

1. An AND gate
2. An OR gate
3. A NOR gate

We said in section 5.5.4 that the \(QQ^* = 11\) state for the NOR flip-flop is unreachable. Show that this is the case by constructing a state transition table (see section 4.5) that exhausts all possible states and transitions.

Figure 5.14 shows the inputs and outputs of a NAND gate-based debouncing circuit. Using the same \(\overline{S}\) and \(\overline{R}\) data, sketch the outputs \(Q\) and \(Q^*\) of the NOR gate-based debouncing circuit shown here.