Computer realization and packaging

The target computer architecture

The T1 target computer, the NI myRIO 1900, is a single-board computer with an ARM architecture. Specifically, the SoC Xilinx Z-7010’s Cortex-A9 (dual) CPUs use the ARMv7-A ISA Arm (2014). Although we focus on the ARM architecture, many of the concepts considered in this discussion apply more broadly to processors with other ISAs.

The SoC routes most I/O through an integrated FPGA, which can perform I/O much faster than even a dedicated processor. We can consider the FPGA to be a sort of dedicated processor for handling I/O, although it is a very different sort of device than a general-purpose processor. An integrated FPGA is becoming more common in high-performance real-time computers, but it remains rather uncommon for low-cost computers.

The I/O interfaces are grouped into three connectors with several pins each. The A and B connectors are identical and include pins for analog input (AI) and analog output (AO), digital input (DI) and digital output (DO), and power output. The C connector includes pins with similar functionality, with the primary difference in the inclusion of differential analog I/O and power outputs. These I/O connectors are used to connect to the T1 target system UI, electromechanical, and prototyping subsystems. There is also a USB connector for connection to a development system.