Programming models
ARM instruction set architectures
Instruction set architectures!ARM
A running instance of a program is called a processProcesses, which can be comprised of one or more threadsThreads or tasksTasks.1 As we will see in Section 2.7, scheduling tasks for a computer program is a hard job, and there are special considerations for real-time computing. Add to this the facts that many other resources (e.g., memory) must also be managed and a computer often has multiple programs running simultaneously, and it becomes clear that each individual program cannot manage its own use of shared resources. The software that makes the ultimate decisions for managing computing resources is the operating systemOperating systems. Below the "application level"Application-level programming of a program is the "system-level"System-level programming operating system, which is itself above the "hardware level."
A programmer of a real-time computer must understand the processor from an application-level perspective. A description from this level is called a programming model of the processor. Here, we introduce a programming model for an ARM processor.
A processor has, among its functions, three that are repeated endlessly:
Fetch an instruction from memory.Instructions!fetching
Translate the instruction.Instructions!translating
Execute it.Instructions!executing
Typically, the control unit of the processor fetches instructions from memory and translates them. The control unit directs the datapath to execute the instruction. It does this by means of registersRegisters, which are small, special-purpose units of memory in the datapath. The contents of a register are constantly changing: it might store an instruction, some data queued up from the cache or main memory, the result of an instruction, or other information. Due to registers' extremely limited capacity, anything that needs to be stored for an active program is placed in cache memory, main memory, or (if it is to be stored beyond the execution of the program) secondary memory.
An application-level view of the ARMv7 processor registers has \(13\) general-purposeRegisters!ARM, general-purpose \(32\)-bit registers named R0--R12, and three special-purposeRegisters!ARM, special-purpose registers named SP, LR, and PC (also called R13--R15) Arm (2012).
The stack pointerStack pointers (\mintinline{text}{SP}s)Registers!ARM, special-purpose!stack pointer (\mintinline{text}{SP}) SP (R13) register contains the memory addressMemory!addresses of, and therefore points to, the top of the active stack, which holds data temporarily. The return linkRegisters!ARM, special-purpose!return link (\mintinline{text}{LR}) LR (R14) register is used, for instance, to store the current memory address of the calling program during a subroutine call. The program counterRegisters!ARM, special-purpose!program counter (\mintinline{text}{PC}) PC (R15) register contains the memory address of the current instruction plus \(8\) (bytes)—that is, of two instructions from now.
The general-purpose registers typically hold data, such as integers, floating-point numbers, and characters.
The 32-bit application program status register (APSR)Registers!ARM, application status (application program status register, APSR) stores the program's last-executed instruction return status, primarily in flags Arm (2012):
N: negative condition (e.g., N is \(1\) for a negative two's complement result)
Z: zero condition (e.g., Z is \(1\) for the result of a comparison equal to zero)
C: carry condition (e.g., C is \(1\) for an unsigned overflow2 from addition)
V: overflow condition (e.g., V is \(1\) for a signed overflow from addition)
Q: overflow or saturation condition (e.g., Q is \(1\) from digital signal processing)
They are encoded as single bits. These flags can be tested by the next instruction for conditional execution. A nibble of the APSR stores the GE (meaning "greater-than or equal") flag.
The execution state registersRegisters!ARM, execution state allow special instruction sets, such as Thumb, to be executed; contains special Thumb instructions; and sets the register endian mapping (big-endian or little-endian—see Section 2.5.1).EndiannessLittle-endianBig-endian
We will pay special attention to the ARM version 7-A. The optional ARMv7-A vector floating-point unitRegisters!ARM, vector floating-point extension VFPv3 extension enables the high performance and efficiency of floating-point arithmetic. The extension has its own dedicated extension registers.
Here are some examples of the types of instructions that a processor might encounter:Instructions
Load or store (to/from registers)
Transfer (among registers)
Move (elsewhere in memory)
Set/reset bits
Shift/rotate
Arithmetic operations (add, subtract, multiply, divide, negate)
Logic (ands, ors, etc.)
Conditional branches and jumps
Unconditional branches and jumps
Subroutines
Addressing modes
Processors!addressing modes
Addressing modes specify how the processor is to calculate the memory address for a load or a store operation. For the ARMv7-A ISA, the address is composed of two parts: a base register value and an offset Arm (2012). The base register can be any core ARM register. The offset must have one of the following three formats:
An unsigned number, it can be summed with (or subtracted from) the value of the base register.
A value from a core ARM register other than PC.
A shifted value from a core ARM register other than PC summed with (or subtracted from) the value of the base register.
These lead to the following three addressing modes:
The offset is summed with (or subtracted from) the base register, forming the memory address.
Same as "Offset," with the new address being assigned to the base register.
The memory address is the value of the base register. The base register is then offset.
Addressing modes
Processors!addressing modes
Programming models
ARM instruction set architectures
Instruction set architectures!ARM
In keeping with much of the real-time computing literature, we use the terms "thread" and "task" interchangeably (see Section 6.1).↩︎
Overflow occurs when an integer requires more digits than are available to it in memory. This will become clearer when we discuss numeral systems in Section 2.4.↩︎